TASK #PROJ_006MASTER DIFFICULTY
LLVM IR SIMD Vectorization & Register Allocation RLHF Performance Ranking
Publisher: DeepCode Compilers Inc • 100% Pre-funded Escrow
00:42:00
$44.80 Earned Session
Technical Scope & Verification Criteria
Analyze SSA form LLVM IR instructions (`%vector.body`, `llvm.masked.load`), evaluate loop invariant code motion (LICM), and inspect generated assembly for x86_64 target triples.
Required Deliverable Acceptance Criteria
- Compare cycle counts and vector register usage (zmm0-zmm31) across output pairs.
- Verify instruction legality and alignment correctness (`align 64`).
- Provide detailed written critique for compiler optimization model alignment.